1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and more particularly to a method of fabrication, which eliminates the need for transfer gate sacrificial oxide, thereby reducing the number of process steps in forming metal oxide semiconductor field effect transistors (MOSFETs), improving corner device leakages, reducing process defects, and loss of isolation insulator material.
2. Description of the Related Art
In processing a logic wafer, the initial step is forming an oxide (e.g., typically referred to as a xe2x80x9cpad oxidexe2x80x9d), and thereafter depositing a silicon nitride layer (e.g., typically referred to as a xe2x80x9cpad nitridexe2x80x9d), creating an isolation feature (e.g., a shallow trench isolation, but equally relevant to a field oxide isolation or other means of isolation), and filling the trench with insulator material.
Next, the pad nitride is stripped, typically using a hot phosphoric etch, followed by a hydrofluoric acid (HF) dip, or any oxide removing fluid to remove the pad oxide underneath. After the pad films are removed, a transfer gate sacrificial oxide (e.g., a xe2x80x9cTG Sac Oxxe2x80x9d) is grown to serve as a barrier film, between the Si surface and photoresist, as well as to reduce implant damage during ion implantation. Additionally, the thickness of this sacrificial oxide film is crucial for the threshold voltage control of the MOSFETs.
Finally, after the logic wells are implanted, the TG Sac Ox is stripped using an oxide etchant, and the silicon surface is exposed and cleaned for gate oxide growth.
However, the above-described conventional method is problematic because the combination of these isotropic wet etches for removing the pad nitride, pad oxide, and TG Sac Ox consumes isolation oxides. In STI isolation, the weak points in the TEOS fill create problems for subsequent processing when exposed during prior processing.
For example, trench isolation wafers (e.g., STI) are scrapped for defects called xe2x80x9cseamsxe2x80x9d, which also cause polysilicon-polysilicon features to short electrically. In high aspect ratio isolation trenches, a filling void occurs during the trench fill process which, if exposed to wet etches (particularly oxide etches), creates an indentation in which the seams defect can form. Thus, additional stripping steps result in high product costs due to defective parts. Field oxide isolation processing also has certain defects associated therewith including oxide consumption, leakage, poor insulation and a xe2x80x9ccorner devicexe2x80x9d.
The thermal oxide isotropic etches are particularly harmful for causing the isolation pull-down, the xe2x80x9cseamxe2x80x9d, and xe2x80x9cdivotxe2x80x9d. The divot occurs at a corner of the trench because the wet etches are isotropic, thereby etching laterally and vertically as opposed to the center of the trench, where the directional attack causes xe2x80x9cpulldownxe2x80x9d. As a result, the divots are formed at corners of the trench fill which creates later processing problems by making the surface of the wafer less planar.
The non-planar wafer surface causes photolithography problems, film uniformity issues, and increases the risk of process defects such as PC-PC shorts, or entrapment of foreign material.
In view of the foregoing and other problems of the conventional methods, it is an object of the present invention to provide a method for forming a semiconductor device, in which the transfer gate sacrificial oxide (and resulting step to remove such an oxide) is not required, thereby reducing the number of manufacturing steps, costs, and simultaneously reducing isolation divot/pull-down and associated defects described above.
In a first aspect of the present invention, a method of forming a semiconductor device is provided, which includes steps of forming an oxide layer on a semiconductor substrate, forming a silicon nitride layer on the oxide layer, forming isolation regions in the substrate (e.g., using one lithographic mask and etching through the nitride layer and oxide layer into the substrate), removing the silicon nitride layer, ion implanting dopant ions, while using the initial oxide layer as a screening layer, removing the oxide layer, and forming a gate oxide layer over the semiconductor substrate.
In a second aspect of the present invention, a method for forming an active area of a semiconductor device, is provided which includes steps of defining isolation regions in a substrate, using a pad oxide, left after removing a nitride layer of an oxide/nitride mask stack, for a barrier layer for ion implants formed in the substrate, and forming a gate oxide over the substrate, following defining the isolation regions, implants, and removal of pad oxide, without using a traditionally formed transfer gate sacrificial oxide and without stripping the transfer gate sacrificial oxide.
In a third aspect of the present invention, a method for forming an active area of a semiconductor device, includes using a pad oxide, remaining after removing a film layer thereover of an oxide/film mask stack, for a screen layer for ion implants formed in the substrate, and forming a gate oxide over the substrate, following defining the well implants and stripping pad oxide, without using a sacrificial oxide.
With the unique and unobvious aspects and features of the present invention, the transfer gate sacrificial oxide is eliminated, unlike the conventional process, as described above.
An important feature of the process of the present invention is that the oxide is used in the isolation pad films as the barrier film for the well implants. Using a selective hot phosphoric pad nitride etch or a chemical downstream etch (CDE), the remaining pad oxide can be controlled to the desired thickness for the CMOS device well implants. Specifically, the pad nitride can be removed, leaving a well-controlled, uniform amount of oxide, to be used as an implant screen.
With the invention, an entire oxide strip step is eliminated, which reduces the removal of the isolation fill feature (especially thermal oxide etches). Excessive oxide removals can damage the substrate surface, degrade the gate integrity/reliability, and cause defects, thereby creating complications during subsequent processing.
The present invention also improves seams, polysilicon-to-polysilicon shorts yields, reduces the corner device leakage, and rounds the corners of the trench isolations, all of which have significant MOSFET performance implications.